GPU Design Verification

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices.

The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design.

A strong computer architecture background, preferably in graphics, and a solid foundation

in verification methodology will be leveraged to close testing coverage with high confidence.

The ideal candidate will have 1+ years of relevant experience including:

·      Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is a plus

·      Expertise with HDL simulators and waveform viewers

·      Experience defining coverage space, writing coverage model, analyzing results

·      Experience working under strict schedule deadlines with the ability to manage multiple priorities

·      Graphics architecture and programming (OpenGL/OpenCL) highly desired

·      Strong knowledge of computer architecture, general purpose microprocessor and memory sub-system micro-architecture in lieu of graphics experience.

·      Experience with Perl, Shell scripting, Makefiles, TCL a plus

·      Excellent communication skills and ability to collaborate

As a Graphics Design Verification Engineer, you will be responsible for:

·      Developing verification plans in coordination with design leads and architects

·      Building and maintaining verification test bench components and environments

·      Generating directed and constrained random tests

·      Running simulations and debugging design and environment issues

·      Creating functional coverage points, analyze coverage, and improve test environment to target coverage holes

·      Building automated verification flows for block verification

·      Applying knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs

·      Working with other block and core level engineers to ensure seamless verification flow

BS/MS CE or EE